Communication system providers that design and build data networks continue to provide new equipment that enables operators to provide higher data bandwidths to their customers. At the same time, operating companies purchasing the networking equipment prefer the equipment to be modular, such that the overall communication system is a combination of components that can be easily interchanged and interconnected. Additionally, it is desirable that each new generation of products enables increased data bandwidth in the same size time domain frame as their lower bandwidth predecessors, without increasing the amount of power they consume. Modern communication systems typically are a mosaic of new and old products that are able to function together.
Adding to the mosaic of different components that make up the network, there are currently several standards (specifications) which optical systems may be designed to satisfy that define the transmission and reception specifications for 10G serial data. Examples of such specifications include Multi-Source Agreement (MSA), XENPAC and XFP. These specifications call for circuitry such as SERDES (serializer/deserializer) devices, which could be removed from the optical modules and placed on a system line card to reduce the optical modules, cost and power consumption. This would allow the SERDES devices to be incorporated into devices on the line card, which would increase the overall level of integration.
XFP specifies various electrical characteristics at the module interface, and specifies up to 12 inches of transmission line on FR4 material, an inexpensive PCB material, followed by the SERDES.
However, by integrating the SERDES devices within the line card, the 10 Gbps serial data would then have to be transmitted from the line card to the optical module and this introduces jitter into the signal. The jitter is composed of random and/or deterministic components. The deterministic component is generally caused by bandwidth limitations in the system and is typically data dependent, in the form of ISI (inter-symbol interference). The random jitter is typically low frequency, for example 50 KHz→80 MHz for 10 Gbps SONET applications and is caused by shot noise, flicker noise, or thermal noise in the PLL or the PLL reference all of which convert to phase noise. Other processes that can effect or introduce phase noise include crosstalk from other noise sources and power supply noise.
Systems specifications typically impose rather strict limitations on the amount of jitter that can be generated and injected into optical data being transmitted by the optical module. There are also jitter limitations that apply to the electrical circuits used to drive the optical lasers or optical modulators used for transmission. These limitations lead to the requirement for the bandwidth of the printed circuit board (PCB) and connector over which the data is transmitted from the system to the optical module (and vice versa), to be high enough so as not to impair the data signal by increasing the deterministic jitter. For systems transmitting 10 Gbps serial data and above, the inexpensive connector typically employed to connect the line card to the optical module and lossy PCB material on which the system line card is built significantly limit the transmission bandwidth. As a result the interconnections do not generally support high enough bandwidths and will impair the data signal by increasing its jitter.
It would be desirable for optical modules to provide a low cost, low power-consumption solution to remove the jitter before converting the electrical signal to an optical signal.
One method of re-timing the data is using a CDR (Clock and Data Recovery circuit). The CDR will take the data signal as its input and use it to derive a clock, which can be used to re-time the data. An example is a CDR based on a HOGGE type phase detector or Bang Bang phase detector, both common phase detectors in the art. Because the data is used as a reference for the CDR, this method requires that the data being transmitted from the SERDES device must have low jitter. The CDR will remove any high frequency jitter but will still transfer low frequency jitter. The CDR will not remove any low frequency jitter caused by the SERDES device. Furthermore, since the CDR is not noiseless the output of the CDR will have more jitter than that of the SERDES device because it will transfer the low frequency jitter of the SERDES device and add a small amount of noise of its own to the transmitted data-signal.